Pascal and Francis Bibliographic Databases

Help

Search results

Your search

kw.\*:("dynamic storage")

Document Type [dt]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Publication Year[py]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Discipline (document) [di]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Language

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Author Country

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Results 1 to 25 of 519

  • Page / 21
Export

Selection :

  • and

Raw pointers in application classes of C++ considered HarmfulSMIRNOV, Igor B.ACM SIGPLAN notices. 2007, Vol 42, Num 4, pp 23-30, issn 1523-2867, 8 p.Article

Direct contact PCM―water cold storageMARTIN, Viktoria; BO HE; SETTERWALL, Fredrik et al.Applied energy. 2010, Vol 87, Num 8, pp 2652-2659, issn 0306-2619, 8 p.Article

Effects of microcrystalline cellulose on suspension stability of cocoa beverageYAGINUMA, Yoshihito; KIJIMA, Tsuyoshi.Journal of dispersion science and technology. 2006, Vol 27, Num 7, pp 941-948, issn 0193-2691, 8 p.Article

Beam-induced seeded lateral epitaxy with suppressed impurity diffusion for a three-dimensional DRAM cell fabricationOHKURA, M; KUSUKAWA, K; SUNAMI, H et al.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 2, pp 333-339, issn 0018-9383, 7 p.Article

A 2-υm CMOS 10-MHz microprogrammable signal processing core with an on-chip multiport memory bankWELTEN, F. P. J. M; DELARUELLE, A; VAN WYK, F. J et al.IEEE journal of solid-state circuits. 1985, Vol 20, Num 3, pp 754-760, issn 0018-9200Article

A novel JCMOS dynamic RAM cell for VLSI memoriesELDIN, A. G; ELMASRY, M. I.IEEE journal of solid-state circuits. 1985, Vol 20, Num 3, pp 715-723, issn 0018-9200Article

Charge storage and charge transfer in dynamic memoriesBECKER, J. D.Lecture notes in physics. 1983, Num 196, pp 53-68, issn 0075-8450Article

Circuit autotestable pour la correction d'erreur en mémoire dynamique = Autotestable circuit for the error correction in dynamic memoryGOBBI, J.-M; RAINARD, J.-L.1983, 38 p.Report

MEMOIRE DYNAMIQUEBERDICHEVSKIJ ZM; KAJKOV VN.1976; PRIBORY TEKH. EKSPER.; S.S.S.R.; DA. 1976; NO 3; PP. 80-81; BIBL. 1 REF.Article

A 128 K word×8 bit dynamic RAMSUZUKI, S; NAKAO, M; TAKESHIMA, T et al.IEEE journal of solid-state circuits. 1984, Vol 19, Num 5, pp 624-627, issn 0018-9200Article

Shared word line DRAM cellSCHEUERLEIN, R. E; WALKER, W. W; MORENCY, D. G et al.IEEE journal of solid-state circuits. 1984, Vol 19, Num 5, pp 640-645, issn 0018-9200Article

Trench capacitor leakage in high-density DRAM'sELAHY, M; SHICHIJO, H; CHATTERJEE, P. K et al.IEEE electron device letters. 1984, Vol 5, Num 12, pp 527-530, issn 0741-3106Article

PROPOSED PROCESS MODIFICATIONS FOR DYNAMIC BIPOLAR MEMORY TO REDUCE EMITTER-BASE LEAKAGE CURRENTANTIPOV I.1980; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1980; VOL. 15; NO 4; PP. 714-719; BIBL. 14 REF.Article

SYSTEME D'ELEMENTS DYNAMIQUES D'UNE MEMOIRE ANALOGIQUEBUSSKIJ VI; MALEVICH IA.1976; PRIBORY TEKH. EKSPER.; S.S.S.R.; DA. 1976; NO 3; PP. 86-90; BIBL. 3 REF.Article

Dual-operating-voltage scheme for a single 5-V 16-Mbit DRAMHORIGUCHI, M; AOKI, M; TANAKA, H et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1128-1132, issn 0018-9200Article

A 256K-bit dynamic RAM with high alpha immunityENDO, A; ITO, S; ISHIHARA, M et al.Microelectronics. 1984, Vol 15, Num 5, pp 5-15, issn 0026-2692Article

Dynamic parallel memoriesVISHKIN, U; WIDGERSON, A.Information and control. 1983, Vol 56, Num 3, pp 174-182, issn 0019-9958Article

DYNAMIC MEMORIES OFFER ADVANTAGES.WINFIELD J.1977; ELECTRON. DESIGN; U.S.A.; DA. 1977; VOL. 25; NO 14; PP. 66-70; BIBL. 2 REF.Article

A high speed dual port memory with simultaneous serial and random mode access for video applicationsPINKHAM, R; REDWINE, D. J; VALENTE, F. A et al.IEEE journal of solid-state circuits. 1984, Vol 19, Num 6, pp 999-1007, issn 0018-9200Article

SINGLE-SUPPLY 16-K, 64-K RAMS SIMPLIFY UPGRADINGSMITH F; YU R.1980; ELECTRON. DESIGN; USA; DA. 1980; VOL. 28; NO 11; PP. 85-88Article

EINSATZ VON DYNAMISCHEN RAMS IN ARBEITSSPEICHERN = MISE EN OEUVRE DES MEMOIRES DYNAMIQUES A ACCES DIRECTWITTGRUBER F; HEINZERLING H.1980; ELEKTRONIK; DEU; DA. 1980; VOL. 29; NO 2; PP. 56-58; BIBL. 11 REF.Article

CIRCUITOS INTEGRADOS MOS DE MEMORIAS DINAMICAS.RODRIGUEZ CUBERO V.1976; REV. TELEGR. ELECTRON.; ARGENT.; DA. 1976; VOL. 65; NO 768; PP. 770-772Article

A 60 ns 256 K×l bit DRAM using LD3 technology and double-level metal interconnectionKERTIS, R. A; FITZPATRICK, K. J; OHRI, K. B et al.IEEE journal of solid-state circuits. 1984, Vol 19, Num 5, pp 585-590, issn 0018-9200Article

DYNAMIC R.A.M. TESTING IN THE 80 SBROWN D.1980; NEW ELECTRON.; ISSN 0047-9624; GBR; DA. 1980; VOL. 13; NO 20; PP. 140-142; 2 P.Article

SEMICONDUCTOR MEMORIESWILCOCK JD.1980; NEW ELECTRON.; GBR; DA. 1980; VOL. 13; NO 4; PP. 106-113; (5 P.)Article

  • Page / 21